1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a method for forming a liner and cap layer for placeholder source/drain contact structure planarization and replacement.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In some applications, fins for FinFET devices are formed such that the fins are laterally spaced apart from one another with an isolation material positioned between the fin and above the substrate. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 105 at an intermediate point during fabrication. In this example, the FinFET device 100 includes three illustrative fins 110, an isolation material 130, a gate structure 115, sidewall spacers 120 and a gate cap layer 125. The fins 110 have a three-dimensional configuration: a height, a width, and an axial length. The portions of the fins 110 covered by the gate structure 115 are the channel regions of the FinFET device 100, while the portions of the fins 110 positioned laterally outside of the spacers 120 are part of the source/drain regions of the device 100. Although not depicted, the portions of the fins 110 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition.
The gate structure 115 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 100. The fins 110 have a three-dimensional configuration. The portions of the fins 110 covered by the gate structure 115 is the channel region of the FinFET device 100. In a conventional process flow, additional epitaxial grown semiconductor material may be formed on the portions of the fins 110 that are positioned outside of the spacers 120, i.e., the fins in the source/drain regions of the device 100 may have a merged, unmerged and or embedded condition. Forming the additional epi material on the fins 110 in the source/drain regions of the device reduces the resistance of source/drain regions and/or makes it easier to establish electrical contact to the source/drain regions.
FIG. 1B illustrates a cross-sectional view of the device 100 taken across the fins in the source/drain regions of the devices in a direction corresponding to the gate width direction of the devices. The fins 110 shown in FIG. 1A are so-called densely-spaced fins. An additional so-called isolated fin 135 is illustrated representing a different region of the substrate 105 where the spacing between adjacent fins is larger. For example, the densely-spaced fins 110 may be part of a logic device or SRAM NFET, while the isolated fin 135 may be part of an SRAM PFET. Epitaxial material 140, 145 is formed on the fins 110, 135, respectively. A contact etch stop layer 148 is formed above the dielectric layer 130 and the epitaxial material 140, 145.
Placeholder contact structures 150 with cap layers 155 were formed above the fins 110, 135 by performing deposition and etching processes. Subsequently, a dielectric layer 160 was formed to fill the spaces between the placeholder contact structures 150 and planarized to expose the cap layers 155. One material used for the dielectric layer 160 is SiOC due to its favorable gap filling characteristics and its resistance to CD loss during the removal of the placeholder material 150 and/or the contact etch stop layer 148 for the contact replacement process. However, the removal rate for SiOC planarization is limited by the chemical properties of the material and the slurry used. A lower removal rate reduces polishing uniformity across the wafer, especially in regions with different contact densities.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.